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High-level synthesis
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41	The High-Level Event on Women’s Empowerment and Sustainable Development Post-2015 and Beijing+20: Women’s Economic Empowerment and Sustainable Development – the Synthesis for Success Date: March 2, Monday Venue: Na Add to Reading List Source URL: eu2015.lv Language: English - Date: 2015-02-27 06:22:35 Andris Piebalgs United Nations Industrial Development Organization Latvia International relations United Nations Europe Imants
42	LusSy: an open Tool for the Analysis of Systems-on-aChip at the Transaction Level Matthieu Moy∗ , Florence Maraninchi* , Laurent Maillet-Contoz† Abstract. We describe a toolbox for the analysis of Systems-on-a-chip w Add to Reading List Source URL: www-verimag.imag.fr Language: English - Date: 2007-12-17 11:12:12 Electronic design automation SystemC Logic design Transaction-level modeling High-level synthesis VHDL Advanced Learning and Research Institute Verilog Catapult C Electronic engineering Hardware description languages Digital electronics
43	Datasheet Mobile Devices Solution Overview Designers face numerous challenges in developing the systems and ICs needed for today’s leading-edge mobile Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 12:44:17 Electronic design automation Electronic design Hillsboro Oregon Synopsys Integrated circuit design High-level synthesis Field-programmable gate array Functional verification Application-specific integrated circuit Electronic engineering Electronics Integrated circuits
44	LusSy: A Toolbox for the Analysis of Systems-on-a-Chip at the Transactional Level M. Moy STMicroelectronics, Verimag Add to Reading List Source URL: www-verimag.imag.fr Language: English - Date: 2005-05-13 07:59:35 Hardware verification languages SystemC High-level synthesis Dataflow programming E SpecC Scheduling Catapult C Transaction-level modeling Electronic engineering Electronic design automation Hardware description languages
45	Lattice ispEXPERT TM Design Solutions for the Universe of ISP PLDs TM Add to Reading List Source URL: www.kolter.de Language: English - Date: 2000-11-12 14:42:23 Electronic design Aldec Synopsys Synplicity VHDL Logic synthesis Verilog Field-programmable gate array High-level synthesis Electronic engineering Electronic design automation Hardware description languages
46	Datasheet Synphony C Compiler High-Level Synthesis from C/C++ to RTL Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:31:02 High-level synthesis Logic synthesis SystemVerilog Synopsys Verilog Clock gating Field-programmable gate array Catapult C Compiler Electronic engineering Electronic design automation Hardware description languages
47	Datasheet DC Ultra Concurrent Timing, Area, Power and Test Optimization Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-03-19 18:15:41 Logic synthesis Physical design High-level synthesis Register-transfer level Placement Quality of results Multi-core processor Synopsys Retiming Electronic engineering Electronic design automation Electronics
48	Origin System Design Methodology and Experience: 1M-gate ASICs and Beyond Ásgeir Th. Eiríksson, John Keen, Alex Silbey, Swami Venkataraman, Michael Woodacre Silicon Graphics Inc., Mountain View, CA Abstract. Add to Reading List Source URL: vintagecomputers.info Language: English - Date: 1999-02-05 11:20:10 SGI Origin Integrated circuit design Logic simulation Standard cell Verilog Physical design High-level synthesis Synopsys R10000 Electronic engineering Digital electronics Electronic design automation
49	Origin System Design Methodology and Experience: 1M-gate ASICs and Beyond Ásgeir Th. Eiríksson, John Keen, Alex Silbey, Swami Venkataraman, Michael Woodacre Silicon Graphics Inc., Mountain View, CA Abstract. Add to Reading List Source URL: www.sgidepot.co.uk Language: English - Date: 2008-04-15 16:23:14 SGI Origin Integrated circuit design Logic simulation Standard cell Verilog Physical design High-level synthesis Synopsys R10000 Electronic engineering Digital electronics Electronic design automation
50	High-level Synthesis of Memory Bound and Irregular Parallel Applications with Bambu Vito Giovanni Castellana, Antonino Tumeo, and Fabrizio Ferrandi High Performance Reconfigurable Computing Application Domain  Several Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2014-08-12 11:13:59 Application programming interfaces Computer memory Kernel Software engineering Central processing unit OpenMP Memory architecture Computing Computer programming Parallel computing

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